In a NAND flash memory, which is a type of semiconductor device, a line and space (L&S) repetitive pattern that has a size close to a resolution limit and is drawn based on a designed rule is used for bit lines or word lines of a memory cell unit.
A pattern of an integrated circuit in the NAND flash memory and the like is exposed by using a photomask. In the exposure of the memory cell unit, although a resolution in the repetitive pattern in a central part of the memory cell unit is high, there is a problem that a resolution in a boundary part at an end portion of the memory cell unit is lowered.
To solve this problem, there is known a method of arranging an auxiliary pattern (Sraf: sub resolution assist feature) or a dummy pattern configured to maintain periodicity on the mask aside from a primary pattern. In this method, for example, the auxiliary pattern is arranged on the mask so that a design pattern dimension coincides with a resist pattern dimension.
Further, with the advancement in miniaturization, in a core circuit unit of a sense amplifier or a row decoder, an L&S pattern drawn based on a design rule having a hard resolution, which is not as stringent as that in the memory cell unit, is likewise present. Furthermore, in the core circuit unit, a wide portion (a contact pad) configured to achieve electrical connection with a signal interconnect line or a power supply interconnect line in an upper layer is required in, e.g., an L&S periodic pattern.
However, in a pattern surrounding portion that disrupts the periodicity of such an L&S pattern, since a lithography margin is reduced, pattern formation is difficult.
Moreover, to provide the contact pad having a width that is several-fold of a pattern pitch in the L&S periodic pattern, a large space must be assured between a interconnect line and the contact pad based on restrictions of an MSR (Multi Space Rule) and the like, and there is a problem that the number of interconnect lines that can be arranged around the contact pad is reduced.